`include "defines.v"

module memwb_reg (
    input  wire                     cpu_clk_25M,
	input  wire                     cpu_rst_n,

	// 来自访存阶段的信息
    input  wire                     mem_mreg,
    input  wire [`ALUOP_BUS    ]    mem_aluop,
	input  wire [`REG_ADDR_BUS  ]   mem_wa,
	input  wire                     mem_wreg,
	input  wire [`REG_BUS       ] 	mem_dreg,
    input  wire [`BSEL_BUS      ]   mem_dre,
	input  wire [`INST_ADDR_BUS]   mem_debug_wb_pc, // 供调试使用的PC值，上板测试时务必删除该信号

	// 送至写回阶段的信息 
    output reg                      wb_mreg,
    output reg [`ALUOP_BUS    ]     wb_aluop,
	output reg  [`REG_ADDR_BUS  ]   wb_wa,
	output reg                      wb_wreg,
	output reg  [`REG_BUS       ]   wb_dreg,
    output reg [`BSEL_BUS      ]    wb_dre,
	output reg  [`INST_ADDR_BUS]    wb_debug_wb_pc  // 供调试使用的PC值，上板测试时务必删除该信号
    );

    always @(posedge cpu_clk_25M) begin
		// 复位的时候将送至写回阶段的信息清0
		if (cpu_rst_n == `RST_ENABLE) begin
		    wb_aluop    <= `ALUOP_ZERO;
		    wb_mreg     <= `FALSE_V;
			wb_wa       <= `REG_NOP;
			wb_wreg     <= `WRITE_DISABLE;
			wb_dreg     <= `ZERO_WORD;
			wb_dre      <= 4'b0000;
			wb_debug_wb_pc        <= `PC_INIT;   // 上板测试时务必删除该语句
		end
		// 将来自访存阶段的信息寄存并送至写回阶段
		else begin
		    wb_aluop    <= mem_aluop;
		    wb_mreg     <= mem_mreg;
			wb_wa 	    <= mem_wa;
			wb_wreg     <= mem_wreg;
			wb_dreg     <= mem_dreg;
			wb_dre      <= mem_dre;
			wb_debug_wb_pc        <= mem_debug_wb_pc;   // 上板测试时务必删除该语句
		end
	end

endmodule